Display panel and active device array substrate thereof

ABSTRACT

A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 98133691, filed Oct.5, 2009. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display panel and an active devicearray substrate thereof, and more particularly to a display panel and anactive device array substrate having a slim border.

2. Description of Related Art

Generally, a display panel is composed of an active device arraysubstrate, an opposite substrate and a display medium. The manufactureof the peripheral circuit on the non-display region (peripheral region)of the active device array, which can be integrated in the chip-on-glassprocess or the chip-on-thin-film process, and the manufacture of theactive device array can be implemented at the same time.

FIG. 1 is a schematic top view of a conventional active device arraysubstrate. FIG. 2 is a partially enlarged schematic diagram of theactive device array substrate depicted in FIG. 1. As shown in FIG. 1 andFIG. 2, the active device array substrate 101 includes a substrate 110,a plurality of scan lines 122, a plurality of data lines 132, aplurality of pixel units 140 and a driving chip 150. The substrate 110has a display region 112 and a non-display region 114, wherein thenon-display region 114 surrounding the display region 112 with borders114 a and 114 b. The scan lines 122 and the data lines 132 cross overeach other so as to form several pixel units 140 within the displayregion 112. The driving chip 150 is located in the non-display region114 of the substrate 110, and the scan lines 122 and the data lines 132are electrically connected to the driving chip 150. Moreover, the datalines 132 are electrically connected to the driving chip 150 through thewire routing of the peripheral circuit at the upper and the lower sidesof the border 114 b.

For instance, in the display panel with the use of the trichromaticcolor (RGB) to adjust the level of the colorfulness and with a 640×480video graphic array resolution, the amount of the scan lines 122 of theaforementioned active device array substrate 101 is 480 (G1, G2, G3 . .. G480) and the amount of the data lines 132 of the aforementionedactive device array substrate 101 is 1920 (640×3=1920, S1, S2, S3 . . .S1920). Therefore, it is necessary for one of the borders at the upperand the lower sides of the display region 112 to have enough space forthe wire routing of the peripheral circuit with 960 data lines(1920/2=960) therein. That is, the active device array substrate 101should have enough border width W for the data lines 132 to beelectrically connected to the driving chip 150. Herein, the border widthW of the active device array substrate 101 is larger than 1.2centimeter.

Due to high demand on smaller dimensions of the display panelapplications such as portable phone and digital camera, how to decreasethe border width W of the active device array substrate 101 in order toimprove the portability of the electronic product becomes an importantissue to be solved immediately.

SUMMARY OF THE INVENTION

The present invention provides an active device array substrate with aslim border capable of increasing the space utilization.

The present invention further provides a display panel comprising theaforementioned active device array substrate capable of reducing theproduction costs and increasing the product portability.

The present invention provides a display panel comprising an activedevice array substrate, an opposite substrate and a display medium. Theactive device array substrate includes a substrate, a plurality of scanlines, a plurality of data lines, a plurality of pixel units and aplurality of data signal transmission lines. The scan lines are disposedparallel to each other on the substrate. The data lines are disposedparallel to each other on the substrate, wherein the scan lines and thedata lines cross over each other so as to define a plurality of pixelregions on the substrate. Each of the plurality of pixel units isdisposed within one of the plurality of pixel regions respectively, andeach of the plurality of pixel units comprises a plurality of sub-pixelunits, and the sub-pixel units within the same pixel unit areelectrically connected to the same data line, and each of the pluralityof sub-pixel units within the same pixel unit is electrically connectedto one of the plurality of the scan lines respectively. The data signaltransmission lines are disposed on the substrate, wherein each of theplurality of data signal transmission lines is electrically connected toone of the plurality of data lines respectively and the extendingdirection of the plurality of data signal transmission lines issubstantially parallel to the extending direction of the plurality ofscan lines. The opposite substrate is disposed above the active devicearray substrate. The display medium is disposed between the oppositesubstrate and the active device array substrate.

According to one embodiment of the present invention, the extendingdirection of the aforementioned plurality of scan lines is substantiallyperpendicular to the extending direction of the plurality of data lines.

According to one embodiment of the present invention, the number of theaforementioned plurality of data signal transmission lines is smallerthan the number of the plurality of scan lines.

According to one embodiment of the present invention, each of theplurality of data signal transmission lines is disposed between twoadjacent rows of the plurality of the pixel units.

According to one embodiment of the present invention, each of theplurality of data signal transmission lines is disposed between twoadjacent rows of the plurality of the sub-pixel units.

According to one embodiment of the present invention, the aforementionedsubstrate has a display region and a non-display region contiguous todisplay region, and the plurality of pixel units are disposed within thedisplay region, and the plurality of the scan lines, the plurality ofthe data lines and the plurality of the data signal transmission linesextend from the display region to the non-display region.

According to one embodiment of the present invention, the aforementionedactive device array substrate further comprises a driving chip disposedon the non-display region, and the driving chip is electricallyconnected to the plurality of scan lines, the plurality of data linesand the plurality of data signal transmission lines.

According to one embodiment of the present invention, the aforementionedactive device array substrate further comprises an integrated gatedriver on array (GOA) disposed on the non-display region, and theintegrated gate driver on array is electrically connected to theplurality of scan lines, the plurality of data lines and the pluralityof data signal transmission lines.

According to one embodiment of the present invention, the driving chipand the integrated gate driver on array are disposed at the same side ofthe plurality of pixel units.

According to one embodiment of the present invention, the driving chipand the integrated gate driver on array are disposed at different sidesof the plurality of pixel units.

The invention also provides an active device array substrate including asubstrate, a plurality of scan lines, a plurality of data lines, aplurality of pixel units and a plurality of data signal transmissionlines. The scan lines are disposed parallel to each other on thesubstrate. The data lines are disposed parallel to each other on thesubstrate, wherein the scan lines and the data lines cross over eachother so as to define a plurality of pixel regions on the substrate.Each of the plurality of pixel units is disposed within one of theplurality of pixel regions respectively, and each of the plurality ofpixel units comprises a plurality of sub-pixel units, and the sub-pixelunits within the same pixel unit are electrically connected to the samedata line, and each of the plurality of sub-pixel units within the samepixel unit is electrically connected to one of the plurality of the scanlines respectively. The data signal transmission lines are disposed onthe substrate, wherein each of the plurality of data signal transmissionlines is electrically connected to one of the plurality of data linesrespectively and the extending direction of the plurality of data signaltransmission lines is substantially parallel to the extending directionof the plurality of scan lines.

According to the above description, since the active device arraysubstrate of the present invention possesses a unique circuit design,the width of the border is decreased and the space utilization isincreased. Moreover, the display panel of the present inventioncomprises the aforementioned active device array substrate so that theproduction cost is decreased and the product portability is increased.

In order to make the aforementioned and other features and advantages ofthe invention more comprehensible, embodiments accompanying figures aredescribed in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic top view of a conventional active device arraysubstrate.

FIG. 2 is a partially enlarged schematic diagram of the active devicearray substrate depicted in FIG. 1.

FIG. 3 is a schematic view of a display panel according to oneembodiment of the present invention.

FIG. 4 is a schematic top view illustrating an active device arraysubstrate of the display panel in FIG. 3.

FIG. 5 is a partial schematic view of FIG. 4.

FIG. 6 is a partially enlarged schematic diagram of FIG. 5.

FIG. 7 is a partially enlarged schematic diagram illustrating an activedevice array substrate according to another embodiment of the presentinvention.

FIG. 8 is a schematic top view illustrating an active device arraysubstrate according to one embodiment of the present invention.

FIG. 9 is a schematic top view illustrating an active device arraysubstrate according to one embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 3 is a schematic view of a display panel according to oneembodiment of the present invention. As shown in FIG. 3, a display panel200 includes an active device array substrate 201, an opposite substrate203 and a display medium 205. The opposite substrate 203 is disposedabove the active device array substrate 201. The display medium 205 isdisposed between the opposite substrate 203 and the active device arraysubstrate 201. The display panel 200 can be, for example, a liquidcrystal display panel, an organic light emitting display panel, anelectrophoretic display panel or other display panels. The oppositesubstrate 203 can be, for example, a color filter substrate, and thedisplay medium 205 can be, for example, a liquid crystal layer or othermaterials. In the present embodiment, the display panel 200 can be, forexample, a landscape viewing display panel.

FIG. 4 is a schematic top view illustrating an active device arraysubstrate of the display panel in FIG. 3. FIG. 5 is a partial schematicview of FIG. 4. FIG. 6 is a partially enlarged schematic diagram of FIG.5. As shown in FIG. 4, FIG. 5 and FIG. 6, furthermore, the active devicearray substrate 201 including a substrate 210, a plurality of scan lines222, a plurality of data lines 232, a plurality of pixel units 240 and aplurality of data signal transmission lines 260.

In the present embodiment, the substrate 210 has a display region 212and a non-display region 214 contiguous to the display region 212. Asfor the active device array substrate 201 shown in FIG. 4, thenon-display region 214 includes a border 214 a at the left-hand side ofthe display region 212 and a border 214 b at the upper and lower sidesof the display region 212. The pixel units 240 are disposed within thedisplay region 212, and the scan lines 222, the data lines 232 and thedata signal transmission lines 260 extend from the display region 212 tothe non-display region 214.

The scan lines 222 are disposed parallel to each other on the substrate210. The data lines 232 are disposed parallel to each other on thesubstrate 210, wherein the scan lines 222 and the data lines 232 crossover each other so as to define a plurality of pixel regions 212 a onthe substrate 210, as shown in FIG. 6. In the present embodiment, theextending direction of scan lines 222 is substantially perpendicular tothe extending direction of the data lines 232.

Moreover, each of the pixel units 240 is disposed within one of thepixel regions 212 a respectively, and each of the pixel units 240comprises three sub-pixel units 242 a, 242 b and 242 c, and thesub-pixel units 242 a, 242 b and 242 c within the same pixel unit 240are electrically connected to the same data line 232, and each of thesub-pixel units 242 a, 242 b and 242 c within the same pixel unit iselectrically connected to one of the scan lines 222 respectively. Thesub-pixel units 242 a, 242 b and 242 c can be, for example, respectivelycorrespond to a red filter layer, a green filter layer and a blue filterlayer (not shown) to display various levels of colorfulness. In summary,the active device array substrate 201 is an active device arraysubstrate with tri-gate driving structure.

Since three sub-pixel units 242 a, 242 b and 242 c within the same pixelunit 240 share the same data line 232 to transmit the corresponding datasignal, under this structure design, the number of the scan lines 222 isincreased and the number of the data lines is decreased. In other words,the number of the source driving chips (not shown) which are bonded tothe active device array substrate 201 can be effectively decreased.Since production cost of the source driving chips is high, the decreasein the number of the source driving chips in use can effectivelydecrease the manufacturing cost. Furthermore, because the signalsprocessed by the source driving chip are relatively complicated andpower-consuming, the less the number of the source driving chips is andthe more the power consumed by the active device array substrate 201 canbe saved.

As shown in FIG. 3, FIG. 4 and FIG. 5, the data signal transmissionlines 260 are disposed on the substrate 210, wherein each of the datasignal transmission lines 260 is electrically connected to one of thedata lines 232 respectively through the corresponding nodes or contactplugs and the extending direction of the data signal transmission lines260 is substantially parallel to the extending direction of the scanlines 222. Herein, the data signal transmission lines 260 can be, forexample, a circuit layout using the multi-layered metal layer anddisposed over the scan lines 222 so that the opening ratio of thedisplay panel 200 can be prevented from being affected. Further, theactive device array substrate 201 further comprises a driving chip 250disposed on the non-display region 214, wherein the driving chip 250 iselectrically connected to the scan lines 222, the data lines 232 and thedata signal transmission lines 260.

In the present embodiment, the number of the data signal transmissionlines 260 is smaller than the number of the scan lines 222. That is,only portions of the data lines 232 are connected to the data signaltransmission lines 260. In the present embodiment, the number of thedata signal transmission lines 260 is one third or two thirds of thenumber of the data lines 232.

For instance, the resolution of the display panel 200 is a 640×480 videographic array resolution, and the active device array substrate 201 isdriven by the aforementioned tri-gate driving structure. Thus, theamount of the data lines 232 of the active device array substrate 201 is640 (S1, S2, S3 . . . S640), and the amount of the scan lines 222 is1440 (480×3=1440, G1, G2, G3 . . . G1440). In the present embodiment,each of the data signal transmission lines 260 can be, for example,disposed between the two adjacent rows of the pixel units 240, and theamount of the data signal transmission lines 260 is 480 (TGP1, TGP2 . .. TGP480). Since the data lines 232 can be electrically connected to thedriving chip 250 through the data signal transmission lines 260, only160 data lines 232 (640−480=160) in the non-display region 214 of theactive device array substrate 201 are needed in the wire routing of theperipheral circuit. In other words, the wire routing at the border 214 bat one of the upper and the lower sides of the active device arraysubstrate 201 only has 80 data lines 232 (160/2=80).

According to the aforementioned circuit design, the active device arraysubstrate 201 of the present invention has a border with a width Wsmaller than 1 millimeter. That is, comparing to the conventional activedevice array substrate 101, the active device array device 201 possessesa relatively slim border 214 b so as to improve the space utilization.Hence, the product applied with the active device array substrate 201possesses a relatively better portability.

FIG. 7 is a partially enlarged schematic diagram illustrating an activedevice array substrate according to another embodiment of the presentinvention. As shown in FIG. 7, in another embodiment, each of the datasignal transmission lines 260 of the active device array substrate 201can be disposed between the two adjacent rows of the sub-pixel units242. That is, the number of the data signal transmission lines 260 canbe further increased to reduce the width W of the border for the wirerouting of the data lines 232. Further, all of the data lines 232 can beeven connected to the data signal transmission lines 260 to achieve theframeless effect.

In some embodiments, the number of the data signal transmission lines260 can be equal to the number of the data lines 232. That is, the datalines 232 can be electrically connected to the driving chip 250completely through the data signal transmission lines 260. In otherwords, the width W of the border of the active device array substrate201 can be further decreased to obtain a better space utilization. Theabove description is only an exemplar and the present invention is notlimited to the number and the location of the data signal transmissionlines 260. People skilled in the art can adjust the number and thelocation of the data signal transmission lines 260 according to thepractical application.

FIG. 8 is a schematic top view illustrating an active device arraysubstrate according to one embodiment of the present invention. As shownin FIG. 8, the active device array substrate 301 possesses allcomponents shown in the active device array substrate 201, whereinidentical elements are referred to by the same reference numbers, anddetailed descriptions thereof are omitted hereinafter.

Further, the active device array substrate 301 further comprises anintegrated gate driver on array (GOA) 370 disposed on the non-displayregion 214, wherein the integrated gate driver on array 370 iselectrically connected to the scan lines 222, the data lines 232 and thedata signal transmission lines 260. It should be noticed that, in theaforementioned active device array substrate 201, because the number ofthe data lines 232 is decreased and the number of the scan lines 222 isincreased, the demands on the gate driving chip (not shown) areincreased. Therefore, in the active device array substrate 301, theconfiguration of the integrated gate driver on array 370 can help todecrease the number of the gate driving chips used by the scan lines 222and further to decrease the manufacturing cost.

Herein, the driving chip 250 and the integrated gate driver on array 370are located at the same side of the pixel units 240. However, thepresent invention is not limited by the aforementioned configuration. Inother embodiments, as shown in FIG. 9, the driving chip 250 and theintegrated gate driver on array 370 of the active device array substrate401 can be located at different sides of the pixel units 240. Therefore,the configurations of the driving chip and the integrated gate driver onarray can be further adjusted according to the actual application.

According to the above description, the active device array substrate ofthe present invention possesses a unique circuit design which candecrease the number of the data lines and the number of the sourcedriving chips. Therefore, the active device array substrate possessesthe advantages including slim border, better space utilization and lowerpower consumption. Moreover, the display panel of the present inventioncomprises the aforementioned active device array substrate so that theproduction cost is decreased and the product portability is increased.

Although the invention has been described with reference to the aboveembodiments, it will be apparent to one of the ordinary skill in the artthat modifications to the described embodiment may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention will be defined by the attached claims not by the abovedetailed descriptions.

What is claimed is:
 1. A display panel, comprising: an active devicearray substrate, wherein the active device array substrate comprises: asubstrate; a plurality of scan lines disposed parallel to each other onthe substrate; a plurality of data lines disposed parallel to each otheron the substrate, wherein the scan lines and the data lines cross overeach other and define a plurality of pixel regions on the substrate; aplurality of pixel units, wherein each of the plurality of pixel unitsis disposed within one of the plurality of pixel regions respectively,and each of the plurality of pixel units comprises a plurality ofsub-pixel units, and the sub-pixel units within the same pixel unit areelectrically connected to the same data line, and each of the pluralityof sub-pixel units within the same pixel unit is electrically connectedto one of the plurality of the scan lines respectively; a plurality ofdata signal transmission lines disposed on the substrate, wherein eachof the plurality of data signal transmission lines is electricallyconnected to one of the plurality of data lines respectively and anextending direction of the plurality of data signal transmission linesis substantially parallel to an extending direction of the plurality ofscan lines, and wherein the number of the plurality of data signaltransmission lines is smaller than the number of the plurality of scanlines, and each of the plurality of data signal transmission lines isdisposed between two adjacent rows of the plurality of the sub-pixelunits; an opposite substrate disposed above the active device arraysubstrate; and a display medium disposed between the opposite substrateand the active device array substrate.
 2. The display panel of claim 1,wherein the extending direction of the plurality of scan lines issubstantially perpendicular to the extending direction of the pluralityof data lines.
 3. The display panel of claim 1, wherein each of theplurality of data signal transmission lines is disposed between twoadjacent rows of the plurality of the pixel units.
 4. The display panelof claim 1, wherein the substrate comprises a display region and anon-display region contiguous to the display region, and the pluralityof pixel units are disposed within the display region, and the pluralityof the scan lines, the plurality of the data lines and the plurality ofthe data signal transmission lines extend from the display region to thenon-display region.
 5. The display panel of claim 4, wherein the activedevice array substrate further comprises a driving chip disposed on thenon-display region, and the driving chip is electrically connected tothe plurality of scan lines, the plurality of data lines and theplurality of data signal transmission lines.
 6. The display panel ofclaim 4, wherein the active device array substrate further comprises anintegrated gate driver on array (GOA) disposed on the non-displayregion, and the integrated gate driver on array is electricallyconnected to the plurality of scan lines, the plurality of data linesand the plurality of data signal transmission lines.
 7. The displaypanel of claim 6, wherein the driving chip and the integrated gatedriver on array are disposed at the same side of the plurality of pixelunits.
 8. The display panel of claim 6, wherein the driving chip and theintegrated gate driver on array are disposed at different sides of theplurality of pixel units.
 9. An active device array substrate,comprising: a substrate; a plurality of scan lines disposed parallel toeach other on the substrate; a plurality of data lines disposed parallelto each other on the substrate, wherein the scan lines and the datalines cross over each other and define a plurality of pixel regions onthe substrate; a plurality of pixel units, wherein each of the pluralityof pixel units is disposed within one of the plurality of pixel regionsrespectively, and each of the plurality of pixel units comprises aplurality of sub-pixel units, and the sub-pixel units within the samepixel unit are electrically connected to the same data line, and each ofthe plurality of sub-pixel units within the same pixel unit iselectrically connected to one of the plurality of the scan linesrespectively; and a plurality of data signal transmission lines disposedon the substrate, wherein each of the plurality of data signaltransmission lines is electrically connected to one of the plurality ofdata lines respectively and an extending direction of the plurality ofdata signal transmission lines is substantially parallel to an extendingdirection of the plurality of scan lines, and wherein the number of theplurality of data signal transmission lines is smaller than the numberof the plurality of scan lines, and each of the plurality of data signaltransmission lines is disposed between two adjacent rows of theplurality of the sub-pixel units.
 10. The active device array substrateof claim 9, wherein the extending direction of the plurality of scanlines is substantially perpendicular to the extending direction of theplurality of data lines.
 11. The active device array substrate of claim9, wherein each of the plurality of data signal transmission lines isdisposed between two adjacent rows of the plurality of the pixel units.12. The active device array substrate of claim 9, wherein the substratecomprises a display region and a non-display region contiguous to thedisplay region, and the plurality of pixel units are disposed within thedisplay region, and the plurality of the scan lines, the plurality ofthe data lines and the plurality of the data signal transmission linesextend from the display region to the non-display region.
 13. The activedevice array substrate of claim 12 further comprising a driving chipdisposed on the non-display region, wherein the driving chip iselectrically connected to the plurality of scan lines, the plurality ofdata lines and the plurality of data signal transmission lines.
 14. Theactive device array substrate of claim 12 further comprising anintegrated gate driver on array (GOA) disposed on the non-displayregion, wherein the integrated gate driver on array is electricallyconnected to the plurality of scan lines, the plurality of data linesand the plurality of data signal transmission lines.
 15. The activedevice array substrate of claim 14, wherein the driving chip and theintegrated gate driver on array are disposed at the same side of theplurality of pixel units.
 16. The active device array substrate of claim14, wherein the driving chip and the integrated gate driver on array aredisposed at different sides of the plurality of pixel units.
 17. Adisplay panel, comprising: an active device array substrate, wherein theactive device array substrate comprises: a substrate; a plurality ofscan lines disposed parallel to each other on the substrate; a pluralityof data lines disposed parallel to each other on the substrate, whereinthe scan lines and the data lines cross over each other and define aplurality of pixel regions on the substrate; a plurality of pixel units,wherein each of the plurality of pixel units is disposed within one ofthe plurality of pixel regions respectively, and each of the pluralityof pixel units comprises a plurality of sub-pixel units, and thesub-pixel units within the same pixel unit are electrically connected tothe same data line, and each of the plurality of sub-pixel units withinthe same pixel unit is electrically connected to one of the plurality ofthe scan lines respectively; a plurality of data signal transmissionlines disposed on the substrate, wherein each of the plurality of datasignal transmission lines is electrically connected to one of theplurality of data lines respectively and an extending direction of theplurality of data signal transmission lines is substantially parallel toan extending direction of the plurality of scan lines, and wherein thenumber of the plurality of data signal transmission lines is smallerthan the number of the plurality of scan lines, and each of theplurality of data signal transmission lines is disposed between twoadjacent rows of the plurality of the pixel units; an opposite substratedisposed above the active device array substrate; and a display mediumdisposed between the opposite substrate and the active device arraysubstrate.
 18. The display panel of claim 17, wherein the extendingdirection of the plurality of scan lines is substantially perpendicularto the extending direction of the plurality of data lines.
 19. Thedisplay panel of claim 17, wherein each of the plurality of data signaltransmission lines is disposed between two adjacent rows of theplurality of the sub-pixel units.
 20. The display panel of claim 17,wherein the substrate comprises a display region and a non-displayregion contiguous to the display region, and the plurality of pixelunits are disposed within the display region, and the plurality of thescan lines, the plurality of the data lines and the plurality of thedata signal transmission lines extend from the display region to thenon-display region.
 21. The display panel of claim 20, wherein theactive device array substrate further comprises a driving chip disposedon the non-display region, and the driving chip is electricallyconnected to the plurality of scan lines, the plurality of data linesand the plurality of data signal transmission lines.
 22. The displaypanel of claim 20, wherein the active device array substrate furthercomprises an integrated gate driver on array (GOA) disposed on thenon-display region, and the integrated gate driver on array iselectrically connected to the plurality of scan lines, the plurality ofdata lines and the plurality of data signal transmission lines.
 23. Thedisplay panel of claim 22, wherein the driving chip and the integratedgate driver on array are disposed at the same side of the plurality ofpixel units.
 24. The display panel of claim 22, wherein the driving chipand the integrated gate driver on array are disposed at different sidesof the plurality of pixel units.
 25. An active device array substrate,comprising: a substrate; a plurality of scan lines disposed parallel toeach other on the substrate; a plurality of data lines disposed parallelto each other on the substrate, wherein the scan lines and the datalines cross over each other and define a plurality of pixel regions onthe substrate; a plurality of pixel units, wherein each of the pluralityof pixel units is disposed within one of the plurality of pixel regionsrespectively, and each of the plurality of pixel units comprises aplurality of sub-pixel units, and the sub-pixel units within the samepixel unit are electrically connected to the same data line, and each ofthe plurality of sub-pixel units within the same pixel unit iselectrically connected to one of the plurality of the scan linesrespectively; and a plurality of data signal transmission lines disposedon the substrate, wherein each of the plurality of data signaltransmission lines is electrically connected to one of the plurality ofdata lines respectively and an extending direction of the plurality ofdata signal transmission lines is substantially parallel to an extendingdirection of the plurality of scan lines, and wherein the number of theplurality of data signal transmission lines is smaller than the numberof the plurality of scan lines, and each of the plurality of data signaltransmission lines is disposed between two adjacent rows of theplurality of the pixel units.
 26. The active device array substrate ofclaim 25, wherein the extending direction of the plurality of scan linesis substantially perpendicular to the extending direction of theplurality of data lines.
 27. The active device array substrate of claim25, wherein each of the plurality of data signal transmission lines isdisposed between two adjacent rows of the plurality of the sub-pixelunits.
 28. The active device array substrate of claim 25, wherein thesubstrate comprises a display region and a non-display region contiguousto the display region, and the plurality of pixel units are disposedwithin the display region, and the plurality of the scan lines, theplurality of the data lines and the plurality of the data signaltransmission lines extend from the display region to the non-displayregion.
 29. The active device array substrate of claim 28 furthercomprising a driving chip disposed on the non-display region, whereinthe driving chip is electrically connected to the plurality of scanlines, the plurality of data lines and the plurality of data signaltransmission lines.
 30. The active device array substrate of claim 28further comprising an integrated gate driver on array (GOA) disposed onthe non-display region, wherein the integrated gate driver on array iselectrically connected to the plurality of scan lines, the plurality ofdata lines and the plurality of data signal transmission lines.
 31. Theactive device array substrate of claim 30, wherein the driving chip andthe integrated gate driver on array are disposed at the same side of theplurality of pixel units.
 32. The active device array substrate of claim30, wherein the driving chip and the integrated gate driver on array aredisposed at different sides of the plurality of pixel units.